1. Field of the invention:
The present invention relates to an analog-to-digital converter, and more particularly, to a pipelined 4-stage ADC with digital gain, and offset control.
2. Description of related art
Analog-to-digital converters are circuits commonly used in communications, instrumentation, and consumer devices. A preferred embodiment of the invention utilizes its design in a video-graphics conversion circuit of a flat-panel monitor. Currently most personal computers utilize video cards that convert digital signals into RGB analog signals for displaying graphics on CRT monitors. It is therefore necessary for flat-panel displays to be able to interface with current video graphics systems. FIG. 1 shows a typical flat-panel video graphics conversion circuit. The flat-panel display requires an analog interface 16 to change the analog RGB signals from the RAMDACs 14 into the digital signals required by the graphics controller 18. The RAMDACs 14 are configured at a pixel rate based on the resolution of the screen to convert the digital signals from the graphics processing engine 12 in the PC graphics card 10 into an analog 256-level pulse amplitude modulated signal which is transmitted along with timing signals to the analog interface 16 of the flat panel display. The analog interface 16, which requires high-speed ADCs to convert the data into a digital format for processing, receives the analog graphics data. During the ADC conversion it is also necessary to alter the offset and gain of the signal for adjusting image quality. In a display device, increasing the gain setting results in an image with more contrast. The offset control is independent for the red, green, and blue channels and serves to shift the entire input range, resulting in a change in image brightness. Therefore a need exists for a high-speed, high resolution ADC with offset and gain control, that has low power consumption.
It is therefore, an object of the present invention to provide a pipelined analog-to-digital converter with offset and gain control. It is also an object to provide a pipelined analog-to-digital converter that has reduced power consumption.
To accomplish these and other objects of the present invention, a 4 stage pipelined analog-to-digital converter with a programmable gain stage is provided. The programmable gain stage comprises two capacitor arrays that serve as digital-to-analog converters. Each capacitor array is composed of a binary-weighted section that is further composed of two stages capacitively coupled together to reduce the capacitor ratios. An input analog signal is inputted to a programmable gain stage wherein the offset and gain of the signal can be manipulated using a digital control. A fully differential signal is then sent to the first stage of the pipeline ADC. The first stage outputs a 1.5 bit digital output and provides an extra gain of 2 to the signal. The extra gain allows the programmable gain stage to use less power, and therefore less power consumption in the overall circuit. The second and third stages each provide 2.5 bit digital outputs each. The final stage provides a 3 bit digital output.
It is to be understood that both the foregoing general description and the following detailed description are exemplary, and are intended to provide further explanation of the invention as claimed.